Selasa, 16 Desember 2008

superscalar vs superpipeline

RISC vs CISC

The simplest way to examine the advantages and disadvantages of RISC architecture is by contrasting it with it’s predecessor: CISC (Complex Instruction Set Computers) architecture. Multiplying Two Numbers in Memory
On the right is a diagram representing the storage scheme for a generic computer. The main memory is divided into locations numbered from (row) 1: (column) 1 to (row) 6: (column) 4. The execution unit is responsible for carrying out all computations. However, the execution unit can only operate on data that has been loaded into one of the six registers (A, B, C, D, E, or F). Let’s say we want to find the product of two numbers - one stored in location 2:3 and another stored in location 5:2 - and then store the product back in the location 2:3.
The CISC Approach
The primary goal of CISC architecture is to complete a task in as few lines of assembly as possible. This is achieved by building processor hardware that is capable of understanding and executing a series of operations. For this particular task, a CISC processor would come prepared with a specific instruction (we’ll call it “MULT”). When executed, this instruction loads the two values into separate registers, multiplies the operands in the execution unit, and then stores the product in the appropriate register. Thus, the entire task of multiplying two numbers can be completed with one instruction:

MULT 2:3, 5:2 MULT is what is known as a “complex instruction.” It operates directly on the computer’s memory banks and does not require the programmer to explicitly call any loading or storing functions. It closely resembles a command in a higher level language. For instance, if we let “a” represent the value of 2:3 and “b” represent the value of 5:2, then this command is identical to the C statement “a = a * b.”

One of the primary advantages of this system is that the compiler has to do very little work to translate a high-level language statement into assembly. Because the length of the code is relatively short, very little RAM is required to store instructions. The emphasis is put on building complex instructions directly into the hardware.

The RISC Approach
RISC processors only use simple instructions that can be executed within one clock cycle. Thus, the “MULT” command described above could be divided into three separate commands: “LOAD,” which moves data from the memory bank to a register, “PROD,” which finds the product of two operands located within the registers, and “STORE,” which moves data from a register to the memory banks. In order to perform the exact series of steps described in the CISC approach, a programmer would need to code four lines of assembly:

LOAD A, 2:3
LOAD B, 5:2
PROD A, B
STORE 2:3, A

At first, this may seem like a much less efficient way of completing the operation. Because there are more lines of code, more RAM is needed to store the assembly level instructions. The compiler must also perform more work to convert a high-level language statement into code of this form.

CISC RISC
Emphasis on hardware Emphasis on software
Includes multi-clock
complex instructions
Single-clock,
reduced instruction only
Memory-to-memory:
“LOAD” and “STORE”
incorporated in instructions
Register to register:
“LOAD” and “STORE”
are independent instructions
Small code sizes,
high cycles per second
Low cycles per second,
large code sizes
Transistors used for storing
complex instructions
Spends more transistors
on memory registers

However, the RISC strategy also brings some very important advantages. Because each instruction requires only one clock cycle to execute, the entire program will execute in approximately the same amount of time as the multi-cycle “MULT” command. These RISC “reduced instructions” require less transistors of hardware space than the complex instructions, leaving more room for general purpose registers. Because all of the instructions execute in a uniform amount of time (i.e. one clock), pipelining is possible.

Separating the “LOAD” and “STORE” instructions actually reduces the amount of work that the computer must perform. After a CISC-style “MULT” command is executed, the processor automatically erases the registers. If one of the operands needs to be used for another computation, the processor must re-load the data from the memory bank into a register. In RISC, the operand will remain in the register until another value is loaded in its place.

The Performance Equation
The following equation is commonly used for expressing a computer’s performance ability:

The CISC approach attempts to minimize the number of instructions per program, sacrificing the number of cycles per instruction. RISC does the opposite, reducing the cycles per instruction at the cost of the number of instructions per program. RISC Roadblocks
Despite the advantages of RISC based processing, RISC chips took over a decade to gain a foothold in the commercial world. This was largely due to a lack of software support.

Although Apple’s Power Macintosh line featured RISC-based chips and Windows NT was RISC compatible, Windows 3.1 and Windows 95 were designed with CISC processors in mind. Many companies were unwilling to take a chance with the emerging RISC technology. Without commercial interest, processor developers were unable to manufacture RISC chips in large enough volumes to make their price competitive.

Another major setback was the presence of Intel. Although their CISC chips were becoming increasingly unwieldy and difficult to develop, Intel had the resources to plow through development and produce powerful processors. Although RISC chips might surpass Intel’s efforts in specific areas, the differences were not great enough to persuade buyers to change technologies.

The Overall RISC Advantage
Today, the Intel x86 is arguable the only chip which retains CISC architecture. This is primarily due to advancements in other areas of computer technology. The price of RAM has decreased dramatically. In 1977, 1MB of DRAM cost about $5,000. By 1994, the same amount of memory cost only $6 (when adjusted for inflation). Compiler technology has also become more sophisticated, so that the RISC use of RAM and emphasis on software has become ideal.

processor super scalar

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Superscalar

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Simple superscalar pipeline. By fetching and dispatching two instructions at a time, a maximum of two instructions per cycle can be completed.

Processor board of a CRAY T3e supercomputer with four superscalar Alpha 21164 processors

A superscalar CPU architecture implements a form of parallelism called instruction-level parallelism within a single processor. It thereby allows faster CPU throughput than would otherwise be possible at the same clock rate. A superscalar processor executes more than one instruction during a clock cycle by simultaneously dispatching multiple instructions to redundant functional units on the processor. Each functional unit is not a separate CPU core but an execution resource within a single CPU such as an arithmetic logic unit, a bit shifter, or a multiplier.

While a superscalar CPU is typically also pipelined, they are two different performance enhancement techniques. It is theoretically possible to have a non-pipelined superscalar CPU or a pipelined non-superscalar CPU.

The superscalar technique is traditionally associated with several identifying characteristics. Note these are applied within a given CPU core.

  • Instructions are issued from a sequential instruction stream
  • CPU hardware dynamically checks for data dependencies between instructions at run time (versus software checking at compile time)
  • Accepts multiple instructions per clock cycle

Contents

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[edit] History

Seymour Cray’s CDC 6600 from 1965 is often mentioned as the first superscalar design. The Intel i960CA (1988) and the AMD 29000-series 29050 (1990) microprocessors were the first commercial single chip superscalar microprocessors. RISC CPUs like these brought the superscalar concept to micro computers because the RISC design results in a simple core, allowing straightforward instruction dispatch and the inclusion of multiple functional units (such as ALUs) on a single CPU in the constrained design rules of the time. This was the reason that RISC designs were faster than CISC designs through the 1980s and into the 1990s.

Except for CPUs used in some battery-powered devices, essentially all general-purpose CPUs developed since about 1998 are superscalar. Beginning with the “P6” (Pentium Pro and Pentium II) implementation, Intel’s x86 architecture microprocessors have implemented a CISC instruction set on a superscalar RISC microarchitecture. Complex instructions are internally translated to a RISC-like “micro-ops” RISC instruction set, allowing the processor to take advantage of the higher-performance underlying processor while remaining compatible with earlier Intel processors.

[edit] From scalar to superscalar

The simplest processors are scalar processors. Each instruction executed by a scalar processor typically manipulates one or two data items at a time. By contrast, each instruction executed by a vector processor operates simultaneously on many data items. An analogy is the difference between scalar and vector arithmetic. A superscalar processor is sort of a mixture of the two. Each instruction processes one data item, but there are multiple redundant functional units within each CPU thus multiple instructions can be processing separate data items concurrently.

Superscalar CPU design emphasizes improving the instruction dispatcher accuracy, and allowing it to keep the multiple functional units in use at all times. This has become increasingly important when the number of units increased. While early superscalar CPUs would have two ALUs and a single FPU, a modern design such as the PowerPC 970 includes four ALUs, two FPUs, and two SIMD units. If the dispatcher is ineffective at keeping all of these units fed with instructions, the performance of the system will suffer.

A superscalar processor usually sustains an execution rate in excess of one instruction per machine cycle. But merely processing multiple instructions concurrently does not make an architecture superscalar, since pipelined, multiprocessor or multi-core architectures also achieve that, but with different methods.

In a superscalar CPU the dispatcher reads instructions from memory and decides which ones can be run in parallel, dispatching them to redundant functional units contained inside a single CPU. Therefore a superscalar processor can be envisioned having multiple parallel pipelines, each of which is processing instructions simultaneously from a single instruction thread.

[edit] Limitations

Available performance improvement from superscalar techniques is limited by two key areas:

  1. The degree of intrinsic parallelism in the instruction stream, i.e. limited amount of instruction-level parallelism, and
  2. The complexity and time cost of the dispatcher and associated dependency checking logic.

Existing binary executable programs have varying degrees of intrinsic parallelism. In some cases instructions are not dependent on each other and can be executed simultaneously. In other cases they are inter-dependent: one instruction impacts either resources or results of the other. The instructions a = b + c; d = e + f can be run in parallel because none of the results depend on other calculations. However, the instructions a = b + c; d = a + f might not be runnable in parallel, depending on the order in which the instructions complete while they move through the units.

When the number of simultaneously issued instructions increases, the cost of dependency checking increases extremely rapidly. This is exacerbated by the need to check dependencies at run time and at the CPU’s clock rate. This cost includes additional logic gates required to implement the checks, and time delays through those gates. Research shows the gate cost in some cases may be nk gates, and the delay cost k2logn, where n is the number of instructions in the processor’s instruction set, and k is the number of simultaneously dispatched instructions. In mathematics, this is called a combinatoric problem involving permutations.

Even though the instruction stream may contain no inter-instruction dependencies, a superscalar CPU must nonetheless check for that possibility, since there is no assurance otherwise and failure to detect a dependency would produce incorrect results.

No matter how advanced the semiconductor process or how fast the switching speed, this places a practical limit on how many instructions can be simultaneously dispatched. While process advances will allow ever greater numbers of functional units (e.g, ALUs), the burden of checking instruction dependencies grows so rapidly that the achievable superscalar dispatch limit is fairly small. — likely on the order of five to six simultaneously dispatched instructions.

However even given infinitely fast dependency checking logic on an otherwise conventional superscalar CPU, if the instruction stream itself has many dependencies, this would also limit the possible speedup. Thus the degree of intrinsic parallelism in the code stream forms a second limitation.

[edit] Alternatives

Collectively, these two limits drive investigation into alternative architectural performance increases such as Very Long Instruction Word (VLIW), Explicitly Parallel Instruction Computing (EPIC), simultaneous multithreading (SMT), and multi-core processors.

With VLIW, the burdensome task of dependency checking by hardware logic at run time is removed and delegated to the compiler. Explicitly Parallel Instruction Computing (EPIC) is like VLIW, with extra cache prefetching instructions.

Simultaneous multithreading, often abbreviated as SMT, is a technique for improving the overall efficiency of superscalar CPUs. SMT permits multiple independent threads of execution to better utilize the resources provided by modern processor architectures.

Superscalar processors differ from multi-core processors in that the redundant functional units are not entire processors. A single processor is composed of finer-grained functional units such as the ALU, integer multiplier, integer shifter, floating point unit, etc. There may be multiple versions of each functional unit to enable execution of many instructions in parallel. This differs from a multicore CPU that concurrently processes instructions from multiple threads, one thread per core. It also differs from a pipelined CPU, where the multiple instructions can concurrently be in various stages of execution, assembly-line fashion.

The various alternative techniques are not mutually exclusive—they can be (and frequently are) combined in a single processor. Thus a multicore CPU is possible where each core is an independent processor containing multiple parallel pipelines, each pipeline being superscalar. Some processors also include vector capability.

[edit] See also

[edit] References

  • Mike Johnson, Superscalar Microprocessor Design, Prentice-Hall, 1991, ISBN 0-13-875634-1
  • Sorin Cotofana, Stamatis Vassiliadis, “On the Design Complexity of the Issue Logic of Superscalar Machines”, EUROMICRO 1998: 10277-10284
  • Steven McGeady, “The i960CA SuperScalar Implementation of the 80960 Architecture”, IEEE 1990, pp. 232-240
  • Steven McGeady, et al., “Performance Enhancements in the Superscalar i960MM Embedded Microprocessor,” ACM Proceedings of the 1991 Conference on Computer Architecture (Compcon), 1991, pp. 4-7

[edit] External links

Minggu, 30 November 2008

Pembaca kartu memori



Pembaca kartu memori (bahasa Inggris: memory card reader atau cukup card reader saja) adalah alat untuk membaca kartu memori yang biasanya dihubungkan ke komputer dengan kabel USB.

Pada awalnya pembaca kartu memori dirancang hanya untuk membaca satu jenis kartu memori saja, misalnya hanya kartu CF saja atau kartu SD saja. Kini banyak didapati memory card reader yang dapat membaca berbagai jenis kartu memori, alat ini sering disebut dengan Multicard reader.

USB flash drive


USB flash drive adalah alat penyimpanan data memori flash tipe NAND yang memiliki alat penghubung USB yang terintegrasi. Flash drive ini biasanya berukuran kecil, ringan, serta bisa dibaca dan ditulisi dengan mudah. Per November 2006, kapasitas yang tersedia untuk USB flash drive ada dari 128 megabyte sampai 64 gigabyte.

USB flash drive memiliki banyak kelebihan dibandingkan alat penyimpanan data lainnya, khususnya disket atau cakram padat. Alat ini lebih cepat, kecil, dengan kapasitas lebih besar, serta lebih dapat diandalkan (karena tidak memiliki bagian yang bergerak) daripada disket.
Daftar isi
[sembunyikan]

* 1 USB Flash Drive dalam Windows
* 2 Lihat pula
* 3 Pranala luar
o 3.1 Aplikasi keydrive
o 3.2 Situs-situs HOWTO
o 3.3 Distribusi GNU/Linux untuk USB

 USB Flash Drive dalam Windows




Sistem operasi Microsoft Windows mengimplementasikan USB flash drive sebagai USB Mass Storage Device, dan menggunakan device driver usbstor.sys. Karena memang Windows memiliki fitur auto-mounting, dan USB flash drive merupakan sebuah perangkat plug and play, Windows akan mencoba menjalankannya sebisa mungkin sesaat perangkat tersebut dicolokkan ke dalam soket USB. Windows XP dan yang sesudahnya bahkan memiliki fitur Autoplay, yang mengizinkan flash drive tersebut diakses secara keseluruhan untuk menentukan apa isi dari USB flash drive tersebut.

Akhir-akhir ini, banyak virus komputer lokal seperti halnya Brontok/RontokBro, PendekarBlank, dan virus lokal lainnya menggunakan USB flash drive sebagai media transmisi virus dari satu inang ke inang lainnya, menggantikan disket. Virus-virus yang sebagian besar berjalan di atas Windows tersebut akan semakin cepat beredar ketika memang Windows mengakses drive teserbut menggunakan fitur autoplay yang dimiliki oleh Windows. Karenanya, ada baiknya untuk menonaktifkan fitur autoplay, meski hal ini kurang begitu membantu mencegah penyebaran virus.

RAM



Memori akses acak (bahasa Inggris: Random access memory, RAM)
adalah sebuah tipe penyimpanan komputer yang isinya dapat diakses dalam waktu yang tetap tidak memperdulikan letak data tersebut dalam memori. Ini berlawanan dengan alat memori urut, seperti tape magnetik, disk dan drum, di mana gerakan mekanikal dari media penyimpanan memaksa komputer untuk mengakses data secara berurutan.

Pertama kali dikenal pada tahun 60'an. Hanya saja saat itu memori semikonduktor belumlah populer karena harganya yang sangat mahal. Saat itu lebih lazim untuk menggunakan memori utama magnetic.

Perusahaan semikonduktor seperti Intel memulai debutnya dengan memproduksi RAM , lebih tepatnya jenis DRAM.

Biasanya RAM dapat ditulis dan dibaca, berlawanan dengan memori-baca-saja (read-only-memory, ROM), RAM biasanya digunakan untuk penyimpanan primer (memori utama) dalam komputer untuk digunakan dan mengubah informasi secara aktif, meskipun beberapa alat menggunakan beberapa jenis RAM untuk menyediakan penyimpanan sekunder jangka-panjang.

Tetapi ada juga yang berpendapat bahwa ROM merupakan jenis lain dari RAM, karena sifatnya yang sebenarnya juga Random Access seperti halnya SRAM ataupun DRAM. Hanya saja memang proses penulisan pada ROM membutuhkan proses khusus yang tidak semudah dan fleksibel seperti halnya pada SRAM atau DRAM. Selain itu beberapa bagian dari space addres RAM ( memori utama ) dari sebuah sistem yang dipetakan kedalam satu atau dua chip ROM.




Daftar isi
1 Tipe umum RAM
2 Tipe tidak umum RAM
3 Produsen peringkat atas RAM
4 Pranala luar


Tipe umum RAM
Beberapa jenis RAM. Dari atas ke bawah: DIP, SIPP, SIMM 30 pin, SIMM 72 pin, DIMM, DDR DIMM.SRAM atau Static RAM
NV-RAM atau Non-Volatile RAM
DRAM atau Dynamic RAM
Fast Page Mode DRAM
EDO RAM atau Extended Data Out DRAM
XDR DRAM
SDRAM atau Synchronous DRAM
DDR SDRAM atau Double Data Rate Synchronous DRAM sekarang (2005) mulai digantikan dengan DDR2
RDRAM atau Rambus DRAM

Tipe tidak umum RAM
Dual-ported RAM
Video RAM, memori port-ganda dengan satu port akses acak dan satu port akses urut. Dia menjadi populer karena semakin banyak orang membutuhkan memori video. Lihat penjelasan dalam Dynamic RAM.
  • WRAM
  • MRAM
  • FeRAM




Produsen peringkat atas RAM
  1. Infineon
  2. Hynix
  3. Samsung
  4. Micron
  5. Rambus
  6. Corsair